Power semiconductor elements, i.e., power devices, are key devices in power electronic circuits having frequency/voltage/current control and conversion functions and continuous efforts are made to reduce power loss of the power devices. The power devices include transistors and diodes, and transistors include metal-oxide-semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) while diodes include pin diodes and Schottky barrier diodes (SBDs), and an optimum element is used depending on the operating frequency, voltage, and current.
For example, taking a Schottky barrier diode (SBD) as an example, the structure of the power device is made up of a drift layer playing a role of a high withstand voltage region retaining high withstand voltage, a substrate with mechanical strength, anode metal having an optimum Schottky barrier disposed on the front side, and cathode metal having ohmic contact with a semiconductor region deposed on the back side.
FIG. 1 is a schematic cross-sectional view of an example of a structure of a Schottky barrier diode (SBD) using silicon carbide (4H—SiC) for a substrate. In FIG. 1, reference numeral 1 denotes an SiC substrate; reference numeral 2 denotes an n-type epitaxial layer acting as the drift layer grown on the SiC substrate 1; reference numeral 3 is a junction barrier Schottky (JBS) structure consisting of a p-type region formed by aluminum (Al) ion implantation; reference numeral 4 denotes a peripheral edge portion of an active region consisting of a p-type region formed for the purpose of improving the element withstand voltage; reference numeral 5 denotes a field oxide film consisting of a thermal oxide film (deposition oxide film) formed on the front side of the substrate 1; reference numeral 6 is an ohmic electrode (ohmic alloy layer) disposed on the back surface of the SiC substrate 1; reference numeral 7 denotes a Schottky electrode disposed on the front surface of the SiC substrate 1; reference numeral 8 denotes an Al electrode for bonding with an Al wire disposed on the front surface of the SiC substrate 1; and reference numeral 9 denotes lamination metal for improving adhesiveness with solder.
During conduction when current is applied from an anode to a cathode in such a Schottky barrier diode (SBD), each of the constituent elements acts as resistance and the sum of the resistance in terms of a unit area is referred to as on-resistance. Drift layer resistance accounting for a large proportion of the on-resistance is inversely proportional to the cube of insulation breakdown field intensity specific to semiconductor material. Silicon carbide with 4H type crystal architecture (4H—SiC) has a large band gap of 3.25 eV and therefore, has an insulation breakdown field intensity of 2 to 3 MV/cm, which is about ten times larger than insulation breakdown field intensity of silicon (Si) (0.2 to 0.3 MV/cm), which has been widely used. Therefore, if the 4H—SiC semiconductor is used, the drift layer resistance can be suppressed to several hundredths as compared to silicon semiconductors. A power device using the 4H—SiC semiconductor also has high thermal conductivity characteristics facilitating heat radiation and therefore, is expected as a next-generation low-loss power device (see, e.g., Patent Document 1).
However, although the drift layer resistance can be reduced significantly by using the 4H—SiC semiconductor, if the drift layer resistance is reduced, other resistance components then become conspicuous. One of the components is a substrate resistance. The 4H—SiC semiconductor generally has a specific resistance of 20 mΩcm and a thickness of 350 μm and therefore is resistance of about 0.7 mΩcm2. Since a power device with the drift resistance on the order of 600 to 1200 V has a substrate resistance of 1 to 2 mΩcm2, it is problematic that the substrate resistance is no longer negligible.
A power device mainly made of silicon has the same technical problem. To reduce the contribution of a drift layer to the on-resistance of FZ—Si wafers used as semiconductor substrates, a wafer-thinning process technique has been developed so as to achieve a minimum thickness of the drift layer required for the withstand voltage. The thickness of the drift layer determining the withstand voltage is dependent on a physical property of semiconductor material and, for example, in the case of silicon, the thickness is about 70 μm for withstand voltage of 600 V and about 100 μm for withstand voltage of 1200 V. In development of the semiconductor manufacturing process using FZ—Si wafers, one of the final goals is to establish a technique of processing a thin wafer polished to a thickness necessary for withstand voltage, for example, a wafer with a thickness of about 70 μm and considerable advances have been made such as an improvement in a method of wafer handling for handling a thin wafer (see, e.g., Patent Document 2).
With regard to a silicon carbide semiconductor device using silicon carbide, after a semiconductor layer is deposited and formed on a silicon carbide substrate, the substrate is polished to a thickness equal to or less than 200 μm so as to reduce the on-resistance in a known invention (see, e.g., Patent Document 3). However, Patent Document 3 only discloses a semiconductor device with a thickness of a silicon carbide substrate reduced from 400 μm to about 200 μm and a fabrication method thereof and includes no description about the lower limit of thickness. In a first embodiment described in Patent Document 3, to fabricate a Schottky diode, after an epitaxial growth layer with a thickness of 10 μm is deposited on the silicon carbide substrate, boron ions are implanted to form an impurity layer and an electrode is formed thereon. When the fabrication method disclosed in Patent Document 3 is used, if the thickness of the silicon carbide substrate is made thinner than 200 μm to, for example, a thickness of 100 μm or 50 μm, it is considered that problems such as cracking of the substrate occur as is the case with a manufacturing process using silicon as described above. Therefore, although a semiconductor device with a silicon carbide substrate having a thickness equal to or less than 200 μm is literally disclosed, specifically, Patent Document 3 only discloses a fabrication method of setting a thickness of the silicon carbide substrate to about 200 μm by polishing, etc.
Patent Document 1: Japanese Laid-open Patent Publication No. 2005-5428
Patent Document 2: Japanese Laid-open Patent Publication No. 2005-260267
Patent Document 3: Japanese Laid-open Patent Publication No. 2004-22878
Patent Document 4: Japanese Laid-open Patent Publication No. 2007-243080